1. Field of the Invention
The present invention relates to a multi-port memory for use in image processing.
2. Description of the Prior Art
With reference to FIG. 1, a conventional semiconductor memory is described. In a memory of Q columns.times.S rows (memory array) 1, a row thereof is selected with an output signal of a decoder 2 in accordance with a high order bit AU of an address. By connecting a connection line of a row of the memory 1 to a selector 5 and by controlling the selector 5 with a low order bit AL of the address, read data DO is obtained from the selector 5. The high order bit AU is represented with log N bit. The low order bit AL is represented with log M bit. To simplify the description, FIG. 1 only represents a read mode of the memory array 1.
Recently, a memory suitable for a video signal in accordance with a raster scanning sequence has been proposed. This memory is referred to as a dual-port memory or a video memory. As shown in FIG. 2, this memory is provided with a port for a serial output data SO. In other words, a decoder 2 only outputs a row address. A shift register 6 referred to as SAM serially outputs read data of one row. Thus, serial output data SO is obtained. Normally, row data is loaded to the shift register 6 in parallel at a speed intrinsic to this port.
The port for the output data DO shown in FIG. 1 is referred to as a random access port. The port of the output data SO shown in FIG. 2 is referred to as a serial output port. A memory which is provided with both the ports is referred to as a dual-port memory or a video memory. The dual-port memory is useful in an image processing circuit. However, the image processing circuit may require a plurality of serial output ports. Conventionally, another shift register 6' is disposed at the position represented with a dotted line of FIG. 2 so as to provide two serial output ports. However, so far, it has been difficult to provide four or more serial output ports.
To provide a plurality of serial output ports, as shown in FIG. 3, shift registers SR1, SR2, SR3, and SR4 are connected to the column connection lines of a memory 1 in parallel. These shift registers SR1, SR2, SR3, and SR4 are provided with serial output ports SO1, SO2, SO3, and SO4, respectively. The shift registers SR1, SR2, SR3, and SR4 receive shift clocks SCK1, SCK2, SCK3, and SCK4, respectively. A control circuit 4 supplies parallel load signals LD1, LD2, LD3, and LD4 to the respective shift registers. In addition, high order bits AU1, AU2, AU3, and AU4 in accordance with the respective ports are supplied to a selector 3. With a control signal from a control circuit 4, one of the high order bits is selected.
For example, when the high order bit AU1 is selected by the selector 3, the load signal LD1 is supplied to the shift register SR1. Data of the row accessed with the high order bit AU1 is loaded to the shift register SR1 in parallel. The data of the shift register SR1 is output as serial data SO1 with the shift clock SCK1.
In the construction shown in FIG. 3, the column connection lines should drive the four shift registers SR1, SR2, SR3, and SR4. As the number of shift registers to be driven increases, the load being applied becomes large. Thus, to provide a driver with a large capacity (a buffer circuit), the driver DR1 should have a large area as shown in FIG. 4A. In addition, as shown in FIGS. 4B and 4C, with one driver with an intermediate capacity DR1 and four conventional drivers DR3, the driving capacity can be improved. However, in all of the alternative constructions shown in FIGS. 4A to 4C, the circuit scale becomes large. Thus, it is difficult to provide the drivers in the memory 1. Thus far, a multi-port memory with a large number of serial output ports has not been accomplished.
Moreover, there is another disclosed circuit construction where each port has two stages, a signal being loaded into a first register, an output signal of the first register being input to a second register, and an output signal of the second register being output. This circuit construction is disclosed by the applicant of the present invention as Japanese Patent Application Serial No. HEI 2-173327. In this case, since each port has two stages, the circuit scale disadvantageously becomes large.